An improved Elmore delay model for VLSI interconnects
نویسندگان
چکیده
منابع مشابه
Accurate Analytical Delay Models for VLSI Interconnects
Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. We develop an analytical delay model to incorporate inductance eeects into the delay estima...
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30 b 0 = pl(T new ; b), and q 0 = pl(T new ; v). We now construct ZST T 0 for S by cutting oo the subtree of T rooted at q and replacing it with T new minus the edge between q and z. Since t LD (T 0 ; q) = d(q; s i), it must be that t LD (T 0 ; q) t LD (T; q). If the strict inequality holds, we add extra wire between q and q 0 to enforce equality, and thereby retain zero skew. For convenience, ...
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Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. Here, we develop an analytical delay model based on rst and second moments to incorporate i...
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ژورنال
عنوان ژورنال: Mathematical and Computer Modelling
سال: 2010
ISSN: 0895-7177
DOI: 10.1016/j.mcm.2009.08.024