An improved Elmore delay model for VLSI interconnects

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Accurate Analytical Delay Models for VLSI Interconnects

Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. We develop an analytical delay model to incorporate inductance eeects into the delay estima...

متن کامل

An analytical delay model for RLC interconnects

We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. For the...

متن کامل

5 Conclusions and Directions for Future Work 4.2 Elmore Delay Model 4.1 Linear Delay Model

30 b 0 = pl(T new ; b), and q 0 = pl(T new ; v). We now construct ZST T 0 for S by cutting oo the subtree of T rooted at q and replacing it with T new minus the edge between q and z. Since t LD (T 0 ; q) = d(q; s i), it must be that t LD (T 0 ; q) t LD (T; q). If the strict inequality holds, we add extra wire between q and q 0 to enforce equality, and thereby retain zero skew. For convenience, ...

متن کامل

Analytical Delay Model for RLC Interconnects

Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. Here, we develop an analytical delay model based on rst and second moments to incorporate i...

متن کامل

Crosstalk Noise Model for Shielded Interconnects in VLSI-based Circuits

Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. An analytic model of the peak noise is developed for shielded interconnects based on a model. A design methodology for inserting shields between coupled interconnects to reduce crosstalk noise is presented.

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Mathematical and Computer Modelling

سال: 2010

ISSN: 0895-7177

DOI: 10.1016/j.mcm.2009.08.024